Building a 100k+ Gate Digital Logic Simulator in Rust: Flattening Hierarchies and Maximizing L1 Cache

Short summary

A developer built a 100k+ gate digital logic simulator in Rust using data-oriented design, flattening nested chip hierarchies into a single contiguous array for cache-friendly access. Parallel execution is handled via Tarjan's SCC algorithm for topological depth scheduling, with a dynamic calibration routine that benchmarks single-threaded vs parallel performance to find the optimal crossover threshold per machine. The result is real-time simulation of over 100,000 primitive gates on standard laptop hardware.

• •Flattens nested chip hierarchies into a contiguous array of primitives before simulation starts
• •Uses Tarjan's SCC algorithm for lock-free parallel gate evaluation by topological depth layers
• •Dynamically calibrates single-threaded vs parallel threshold per host machine for optimal performance

Generated with AI, which can make mistakes.